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276 Cards in this Set
- Front
- Back
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Either of the digits 0 or 1, used in the binary number system.
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Binary Digit BIT
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A numeric variable that only represents non-negative numbers (zero or positive numbers).
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Unsigned Integer
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A numeric variable that represents both positive and negative numbers.
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Signed Integer
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A bitwise operation that shifts all the bits of its operand.
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Logical shift
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Shifting left by n bits on a signed or unsigned binary number has the effect of multiplying it by 2^n.
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Shift logical left SHL
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Shifting right by n bits on an unsigned binary number has the effect of dividing it by 2^n (rounding towards 0).
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Shift logical right SHR
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Efficient way of performing multiplication or division of signed integers by powers of two.
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Arithmetic shift
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Shifting left by n bits on a signed or unsigned binary number has the effect of multiplying it by 2^n.
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Shift arithmetic left SAL
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Shifting right by n bits on a two's complement signed binary number has the effect of dividing it by 2^n, but it always rounds down (towards negative infinity).
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Shift arithmetic right SAR
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A substitution cipher used to encode messages by substituting one letter for another a fixed number of positions away in alphabetic location using basic Latin alphabet.
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Caesar Cipher
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moves n bits in the binary to the left then takes each left most bit and inserts on the right.
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Rotate left ROL
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moves n bits in the binary to the right then takes each right most bit and inserts on the left.
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Rotate right ROR
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Established in 1985 by the Institute of Electrical and Electronics Engineers (IEEE); broken into three parts, a sign bit, exponent of base 2, and a fraction called a significand (or coefficient or mantissa).
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IEEE 754 floating-point standard
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international standard-setting body composed of representatives from various national standards organizations.
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International Organization for Standardization ISO
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(2^8 char 256); character-encoding scheme based on the English alphabet that encodes some basic punctuation symbols, some control codes that originated with Teletype machines, 128 specified characters, and a blank space - into the 7-bit binary integers.
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American Standard Code for Information Interchange ASCII
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(2^16 char, 65536); computing industry standard for the consistent encoding, representation and handling of text expressed in most of the world's writing systems, as 16-bit binary integers.
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Unicode
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A continuous signal with potential for an infinite amount of signal resolution.
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Analog signal
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A sequence of discrete signals with a finite number of values.
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Digital signal
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Large; Audio file format standard for storing an audio bitstream on PCs.
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Waveform Audio File Format WAV
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Smaller; Encoding format for digital audio which uses a form of lossy data compression.
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Moving Picture Experts Group version 1 Audio Layer-3 MP3
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Comprises image data as a dot, is the smallest controllable element of a picture represented on the screen.
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Pixel
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Number of distinct pixels in each dimension that can be displayed.
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Resolution (in megapixels)
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Number of bits used for each color component of a single pixel.
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Color depth (in bits)
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Image file format used to store bitmap digital images, independently of the display device (such as a graphics adapter).
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Bitmap BMP
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Image file format that supports lossless data compression; an improved, non-patented replacement for Graphics Interchange Format (GIF), and is the most used lossless image compression format on the Internet.
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Portable Network Graphics PNG
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Encoding information using fewer bits than the original representation.
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Data compression
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ie @E5; form of data compression in which runs of data are stored as a single data value and count, rather than as the original run.
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Run-length encoding RLE
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Data compression algorithms that allows the original data to be perfectly reconstructed from the compressed data.
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Lossless compression
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Data encoding method that compresses data by discarding some of it.
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Lossy compression
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WINDOWS; Archive file format that supports lossless data compression.
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ZIP
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LINUX; Software application used for file compression and decompression.
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GZIP
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One of the earliest electronic computers.
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Electronic Discrete Variable Automatic Computer EDVAC
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Design architecture for an electronic digital computer with subdivisions of a processing unit consisting of ALU and registers, a control unit CU containing an instruction register and program counter, a memory to store both data and instructions, external mass storage, and input and output mechanisms.
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Stored-program Concept
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Hardware within a computer that carries out the instructions of a computer program by performing the basic arithmetical, logical, and input/output operations of the system.
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Central Processing Unit CPU
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Physical devices used to store programs or data on a temporary or permanent basis.
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Memory
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Mechanism through which the computer is fed information.
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Input device
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Mechanism through which the computer conveys the result of a computation.
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Output device
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Instructional model of a computer, created by Dr. Stuart Madnick in 1965.
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Little Man Computer LMC
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sequence of instructions written to perform a specified computer task.
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Software
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tangible computer components.
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Hardware
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Low-level programming language for computers where each statement corresponds to a single machine language instruction.
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Assembly Language
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system of instructions executed directly by a CPU in binary.
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Machine Language
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used to read data from the user up to 3 digits in size.
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Input IN
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used to write data to the user up to three digits in size.
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Output OUT
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performs fetch and execute steps by moving data and addresses between the registers and I/O.
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Control Unit CU
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small amount of storage space used to perform operations on.
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Register
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used for any purpose.
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General Purpose Register GPR
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used for one singular purpose.
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Special Purpose Register SPR
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3 digit GPR used by the arithmetic logic unit (ALU) to execute arithmetic operation and logic decisions also temporarily holds input and output data.
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Accumulator A
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2 digit SPR used to point the Control Unit to the correct memory address of the next instruction.
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Program Counter PC
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3 digit SPR used by the decoder to decode the instruction.
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Instruction Register IR
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2 digit SPR used to point to the correct memory address to read or write.
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Memory Address Register MAR
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3 digit SPR used to hold data to be read or written to the AC or memory. 100 memory locations accepting 3 digits.
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Memory Data Register
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operation to be performed.
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Opcode
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object to be manipulated and may be data or the memory address of data.
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Operand
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A program is loaded into memory in (4) segments. Holds machine code.
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Text/Code Segment
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A program is loaded into memory in (4) segments. Holds data defined within the code.
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Data Segment
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A program is loaded into memory in (4) segments. Holds data of two types: initialized and uninitialized (runtime). These blocks that create variable sized data and uses linked list data structure to identify allocated and unallocated blocks. Memory leak may occur if not unallocated correctly.
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Heap Segment
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A program is loaded into memory in (4) segments. Holds temporary data (ie call/return data) in a last in first out LIFO order. Stack overflow occurs when the caller attempts to use more memory than allocated for the stack.
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Stack Segment
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Segment of code within a program that performs a specific task that is relatively independent of the rest of the program.
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Subroutine
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ARM processor; Byte order (way data is stored in memory) is read left to right and top-down.
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Big Endian
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Intel x86 processor; Byte order (way data is stored in memory) is read right to left and down to up.
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Little Endian
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mechanism for generating values used by the instructions.
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Operand Addressing
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Operand value present in the instruction.
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Immediate
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Effective address of operand in address field.
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Direct
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Operand value located in register.
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Register
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Address field points to address of the actual operand.
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Indirect
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Register contains address of actual operand.
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Register Indirect
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Effective address of operand generated by adding value in address field to contents of a register.
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Indexed or based
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Operand located on stack.
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Stack
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computer with several low-level operations combined into one instruction (Intel x86).
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Complex Instruction Set Computer CISC
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data processing operations can be performed on both the register and memory.
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Register-to-memory architecture
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Intel x86 General Purpose Register - Used with accumulator for arithmetic and logical operations.
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Accumulator AX
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Intel x86 General Purpose Register - Base pointer to the data segment.
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Base BX
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Intel x86 General Purpose Register - A counter for string and loop operations.
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Counter CX
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Intel x86 General Purpose Register - Used in I/O operations for data transfer.
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Data DX
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Intel x86 General Purpose Register - Source pointer for string operations.
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Source SI
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Intel x86 General Purpose Register - Destination pointer for string operations.
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Destination DI
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Intel x86 General Purpose Register - points to top of stack.
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Stack Pointer SP
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Intel x86 General Purpose Register - point to base of stack.
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Stack Base Pointer BP
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Intel x86 Segment Register - points to code.
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Code Segment CS
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Intel x86 Segment Register - points to data.
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Data Segment DS
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Intel x86 Segment Register - points to stack.
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Stack Segment SS
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Intel x86 Segment Register - points to extra data in a tiered approach.
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Extra Segment ES
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Intel x86 Segment Register - used after ES.
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F Segment FS
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Intel x86 Segment Register - used after FS.
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G Segment GS
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report the status of the program being executed (ie OVERFLOW).
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Program Status and Control Register (FLAGS)
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contains a pointer to the next instruction for execution (like PC).
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Instruction Pointer (IP) Register
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interface that allows all software to run on hardware.
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Instruction Set Architecture (ISA)
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Intel x86 Data Type - unsigned integers.
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Fundamental
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Intel x86 Data Type - signed integers.
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Numeric
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Intel x86 Data Type - floating-point.
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Floating-point
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Intel x86 Data Type - allows references to memory locations like info found in MAR.
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Pointer
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Intel x86 Data Type - bits for Boolean values allowing conditional statements.
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Bit field
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Intel x86 Data Type - ASCII.
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String
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Intel x86 Data Type - Single instruction multiple data like video/imaging instruction.
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Packed SIMD
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Intel x86 Instruction Type - MOV
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Data Transfer
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Intel x86 Instruction Type - ADD, SUB, MUL, DIV
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Arithmetic
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Intel x86 Instruction Type - AND, OR, XOR, NOT
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Logical
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Intel x86 Instruction Type - SHL, SAL, SAR, SHL, ROR, ROL
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Bit Manipulation
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Intel x86 Instruction Type - JMP, JGE
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Control Transfer
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Intel x86 Instruction Type - letters, numbers
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String
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Intel x86 Instruction Type - IN, OUT
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I/O
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Intel x86 Instruction Type - multimedia, digital signal processing and graphic processing
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Matrix Math Extensions (MMX)
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Intel x86 Instruction Type - set or clears flag bit with carries.
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Flag
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Intel x86 Instruction Type - allows math operations on floating-point data.
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Floating-point
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Intel x86 Instruction Type - streaming MMX
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Streaming SIMD Extension (SSE)
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Intel x86 Operand Addressing Mode - Operand value in instruction.
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Immediate
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Intel x86 Operand Addressing Mode - Operand value in a register.
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Register
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Intel x86 Operand Addressing Mode - Operand used as pointer to memory address (DIRECT).
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Memory
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Intel x86 Operand Addressing Mode - Loading each segment register and allowing processor to choose correct register based on instruction.
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Segment
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Intel x86 Operand Addressing Mode - Can be directly specified as a static value called displacement, a base, an index, or scale factor, and one or more can be used at a time.
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Offset
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Intel x86 Operand Addressing Mode - Allows assembler or compiler to encode a customized addressing mode.
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Assembler and Compiler
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Intel x86 Operand Addressing Mode - directly address an I/O device.
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I/O Port
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dictate which instructions and architectural features are available.
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Intel x86 Modes of Operation (3)
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Intel x86 Mode of Operation - Used upon power-up and reset of computer system.
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Real-address
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Intel x86 Mode of Operation - Default mode of operations.
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Protected
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Intel x86 Mode of Operation - Allows for transitions between other modes.
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System Management SMM
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Intel x86 Privilege Level - OS kernel.
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Ring 0
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Intel x86 Privilege Level - OS services (device drivers, etc).
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Ring 1 and 2
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Intel x86 Privilege Level - Applications.
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Ring 3
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Data processing operation is only performed in a register and never directly in memory; one instruction for one operation; use a load/store architecture.
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Reduced Instruction Set Computer RISC
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ARM General Purpose Registers - 32-bit ARM GPR's all run fixed-length instruction; less overhead for CPU since length of output already known.
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R0 through R12
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ARM Segment Register - Stack pointer.
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R13 (SP)
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ARM Segment Register - Link Register, used to hold link information.
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R14 (LR)
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ARM Program Status and Control Register - holds status of last instruction such as flags.
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Current Program Status Register (CPSR) or Application...(A...)
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used to save a copy of CPSR when switching modes.
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Save Program Status Register (SPSR)
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ARM Instruction Pointer Register - Program Counter, holds current instruction address.
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R15
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ARM Data Type - byte (8-bit), halfword (16-bit), word (32-bit), double word (64-bit).
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Fundamental
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ARM Data Type - Signed or unsigned integers.
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Numeric
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ARM Data Type - 32-bit pointer.
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Pointer
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ARM Data Type - Two 16-bit integers packed; Four 8-bit integers packed.
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Packed SIMD
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Fixed 32-bit length.
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ARM Instruction Types (5)
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ARM Instruction Type - STO, LDA.
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Data Transfer
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ARM Instruction Type - ADD, ROR
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Arithmetic and Logic
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ARM Instruction Type - Branch, branch with link, and block data transfer instructions allow for control transfer with branch or call.
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Control Transfer
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ARM Instruction Type - Allow transfer of privilege levels and SIMD to include floating-point.
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Flag
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ARM Instruction Type - Media operations like ADD multiple times, concurrently.
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SIMD
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method for generating the memory address used by a load of stored instructions.
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ARM Operand Addressing Modes (4)
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ARM Operand Addressing Mode - useful for accessing structure fields, stack offsets and input/output registers.
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Immediate
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ARM Operand Addressing Mode - useful for accessing arrays or blocks of data.
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Register Indirect
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ARM Operand Addressing Mode - index prior to instruction.
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Pre-indexed
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ARM Operand Addressing Mode - index after instruction.
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Post-indexed
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ARM Mode of Operation - usual ARM program execution state.
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User (Usr)
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ARM Mode of Operation - runs privileged operating system tasks.
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System (sys)
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ARM Mode of Operation - protected mode for the OS.
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Supervisor (svc)
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ARM Mode of Operation - implements virtual memory or memory protection.
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Abort (abt)
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ARM Mode of Operation - supports software emulation of hardware coprocessor.
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Undefined (und)
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ARM Mode of Operation - used to transfer control from non-secure to secure and vice versa by the processor.
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Secure Monitor (mon)
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ARM Mode of Operation - used for general-purpose interrupt handling.
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IRQ (irq)
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ARM Mode of Operation - Fast Interrupt for high-speed transfer.
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FIQ (fiq)
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ARM Privilege Level - user mode indicates an unprivileged execute security state where many features of the architecture are unavailable.
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PL0
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ARM Privilege Level - used by all others besides user where system software will be executed.
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PL1
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Bus - Indicates location data should be read from or written to.
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Address Line
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Bus - Transfers data.
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Data Line
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Bus - Indicates device that has access to bus and what for (interrupts/synchronization).
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Control Line
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Model I/O Configuration - Allows for communication of dissimilar buses to talk (be it different speed or language).
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Bridge
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Model I/O Configuration - Interfaces with processor, memory, and one or more devices (may or may not include its own memory).
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I/O Module
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Model I/O Configuration - Physical way peripheral devices interface with computer; Consists – Control Port determines send or receive, Data Port allows transfer or holds data element, and Status Port obtains flag info.
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Device Interface
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Bus Topology - Logical connection or link between computer systems, categorized by topology.
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Interconnect
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Bus Topology - Connects more than two components together by a control line using master and slave.
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Multipoint Bus
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Connect two components (ie. ALU to CU).
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Point-to-point Bus
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form or means components transmit between sender and receiver.
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Bus Protocol (2)
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sends sequentially one bit at a time (asynchronous), relies on handshaking.
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Serial Communication
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sends sequentially groups of bits via multiple data lines (synchronous), relies on clock in control lines and fixed protocol by clock.
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Parallel Communication
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series of steps used to coordinate asynchronous communication when both sides proceed apace to each step.
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Handshaking
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act of storing data in a region of physical memory called a buffer to hold temporarily while being moved from one place to another.
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Buffering
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system for resolving bus control conflicts and assigning priorities to requests for bus control where there is more than one master.
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Bus Arbitration (4)
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priorities are predetermined.
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Daisy Chain
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centralized master and one or more slaves (IDE bus).
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Centralized Parallel
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highest priority between the devices themselves.
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Distributed using self-selection
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all devices request access, when collisions occur devices request again (ethernet bus).
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Distributed using collision detection
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connects Northbridge to Southbridge.
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Direct Media Interface (DMI)
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attached to Southbridge (SATA is serial).
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Serial Advanced Technology Attachment (SATA)
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connected to Southbridge (serial).
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Universal Serial Bus (USB)
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bus used to connect slow data rate devices such as the Basic I/O System (BIOS).
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Low Pin Count (LPC)
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I/O Control Method - process of periodically checking I/O device status to determine a need to service device (CPU latency high, uses software).
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Programmed I/O
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I/O Control Method - scheme employs interrupts originating from each device.
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Interrupt-driven I/O
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I/O Control Method - Asynchronous event triggered by an I/O device, non-maskables are serious hardware failures.
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Interrupt
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I/O Control Method - Synchronous event triggered by software used to detect overflow.
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Exception
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Exception occurs when memory accessed incorrectly (1/0).
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Faults
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Intentional exceptions.
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Traps
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Exception that reports severe errors (BSD).
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Abort
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unique identification number for Interrupts and Exceptions.
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Vector Number
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vector numbers 0 through 31 are non-maskable while 32 through 255 are maskable.
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Interrupt Descriptor Table (IDT)
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scheme where portions of address space are mapped to memory to speed up data rate.
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Memory-mapped I/O
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mechanism providing device controller ability to transfer data directly to/from memory without involving processor (at cost of hardware complexity).
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Direct Memory Access (DMA) I/O
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Registers, Cache, Primary, Secondary, External
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Memory Hierarchy
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time it takes memory to output set data once the memory controller receives a data request.
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Latency
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main memory bus clock cycles, measures latency until main memory returns data.
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Column Address Strobe (CAS) Latency (CL)
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rate data is loaded from and stored to memory.
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Throughput (Memory Bandwidth)
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small and fast type of storage on the same chip as CPU (multi-core usually more cache, L1, L2, L3).
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Cache Memory
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how it is determined which block of data in cache should be replaced.
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Replacement Policy
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works by keeping history of frequency each block is used, least used is replaced.
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Least Recently Used (LRU)
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Keeps track of oldest block making oldest the victim block and replaced with new block from memory.
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First In, First Out (FIFO)
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Victim is randomly selected, thrashing is highly improbable.
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Random
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Mapping Scheme - Each memory address mapped to one or more cache addresses.
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Direct Mapped
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Mapping Scheme - Allows any memory block to be stored in any cache block (takes more time searching).
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Fully Associative
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policy for updating cache and memory.
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Write Policy
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Updates cache and main memory (RAM) simultaneously during every write.
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Write-through
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Updates the block in main memory when cache block is selected as a victim (possible Page Fault if interrupted).
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Write-back
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instead of transferring only the block needing to be replaced, the blocks around the block needed from memory are also transferred.
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Locality Principle
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operating principle to increase performance by creating levels of cache where L1 is faster but smaller than L2.
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Multi-level Cache
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Independent cache for data and instructions.
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Harvard Cache
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Holds both data and instructions.
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Unified Cache
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used by cache to index data by associating the virtual address (page) to the physical address (frame).
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Transaction Look-aside Buffer (TLB)
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Volatile memory, typically use Synchronous Dynamic Random Access Memory (SDRAM).
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Primary Memory
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allows for reading and writing to.
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Random Access Memory (RAM)
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made up of D flip-flop circuits that hold data only while powered.
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Static RAM (SRAM)
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made up of little batteries/capacitors.
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Dynamic RAM (DRAM)
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reads only.
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Read Only Memory (ROM)
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once programmed, read only and persists without power.
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Programmable ROM (PROM)
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reprogrammable with special tool that emits ultraviolet light to zero out.
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Erasable PROM (EPROM)
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reprogrammable without special tool but erases only one bit at a time.
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Electrically EPROM (EEPROM)
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Erase more than one bit at a time, arrays of NAND and NOR circuits that persist without power. Benefit – no moving parts, faster. Downside – wearing but mitigated with wear leveling.
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Flash Memory (Solid State Drives)
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Non-volatile, usually Magnetic disks.
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Secondary Memory
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multiple platters spin at constant angular velocity (CAV) measured in RPM; tracks are addressed from outside inward from 0; identify sectors through cylinder, head, and sector (CHS) number within set track.
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Magnetic Disk
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time it takes head to move from current track to track with desired data.
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Seek Time
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time for the desired sector of disk to rotate under head.
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Rotational Latency
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time needed to read the sector of data as disk spins below read/write head.
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Transfer Time
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time required for disk to reach operating speed.
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Spin-up Time
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time it takes to retrieve data; sum of seek time + rotational latency + transfer time + spin-up time.
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Disk Access Time
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collection of disks to improve reliability and performance.
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Rodundant Arrays of Independent Disks (RAID)
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performance by using drive spanning to stripe data across many disks; video and image editing.
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RAID 0
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reliability by using disk mirroring; accounting and payroll.
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RAID 1
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reliability and performance by using parity; file, application, email, and web servers.
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RAID 5
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strip of film with magnetic coating; inexpensive medium for abundant data storage but must be accessed sequentially.
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Magnetic Tape
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plastic casing over aluminum film, low power laser reads and writes by creating pits and lands representing 1's and 0's; track read from inside out CCW at constant linear velocity (CLV), motor slows as reaches outside.
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Optical Discs
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low power red laser, stores 700 MB.
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Compact Disc (CD)
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low power red laser, stores 4.7 GB.
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Digital Versatile Disc (DVD)
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low power blue laser, stores 25 GB.
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Blu-ray Disc (BD)
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initial sets of instructions executed in order to find, load, and start a computer's operating system.
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Bootstrap Process
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program stored on ROM chip informs hardware to check themselves.
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Power-on Self Test (POST)
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computer is off then powers on.
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Cold Boot (Hard Boot)
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occurs within OS, when restart is selected; no POST, goes directly to bootstrap loader code.
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Warm Boot (Soft Boot)
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contained in EEPROM chip on motherboard to enable CPU communication with devices.
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Basic Input/Output Services (BIOS)
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chip used to store settings such as boot order, no program code here.
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Complementary Metal-oxide Semiconductor (CMOS)
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part of BIOS program that reads CMOS to find device containing OS.
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Bootstrap Loader
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contained on first physical sector of magnetic disk (sector 0) contains Master Boot Program (MBP), Master Partition Table (MPT), and 2 byte end of sector marker (0x55AA).
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Master Boot Record (MBR)
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446 bytes; will locate and load kernel using MPT identifying the active (bootable) partition.
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Master Boot Program (MBP)
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64 bytes; located in the MBR, made up of 4 entries (16 bytes each) describing each partition on hard disk; ends with 55AA.
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Master Partition Table (MPT)
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Offset =4
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Partition Types
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FAT 12
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0x01
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FAT 16
|
0x0E
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FAT 32
|
0x0C
|
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Linux Native
|
0x83
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Linux Swap
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0x82
|
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BSD/386
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0xA5
|
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Extended
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0x05
|
|
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NTFS
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0x07
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|
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Unknown
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0xDE
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any task done by software can also be done by hardware, and any operation performed directly by hardware can be done using software.
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Principle of Equivalence of Hardware and Software
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digital logic gates in the form of integrated circuits.
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Digital Logic
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the Control Unit and implemented by hardwire or is microprogrammed.
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Control
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x86; program that implements ISA instruction set architecture, and can be changed.
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Microprogrammed
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ARM; complete solution for the CU that implements ISA instruction set architecture.
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Hardwired
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software consists of 1's and 0's make up each instruction.
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Machine Code
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controls executing of programs and protects resources.
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System Software
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human readable language that is one for one with machine code.
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Assembly
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|
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translated to assembly and then one for one into machine code.
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Compiled Languages
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indirectly executed by another program called interpreter and is slower in execution.
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Interpreted Languages
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Multiple instructions that are overlapped in execution.
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Pipelining
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|
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instruction to each stage of the fetch-decode-execute cycle.
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Instruction Level Parallelism (ILP)
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|
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two or more processors on single chip for multiple instructions to execute simultaneously.
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Multicore
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|
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one or more processors transferring instructions from multiple threads; Intel coined HyperThreading.
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Multithreading
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|
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Symmetric Multiprocessing; share a memory to load and store data; bottleneck.
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Shared Memory Systems
|
|
|
Asymmetric Multiprocessing; each CPU has independent memory and coordinates passing messages through interconnect.
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Distributed Shared Memory Systems (Clusters)
|
|
|
all CPUs working on same task reading and writing to same memory, to fuction correctly a lock is placed on current memory.
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Symmetric Multiprocessing
|
|
|
all CPUs interconnected to pass messages to each other otherwise separate process for each by their own memory.
|
Asymmetric Multiprocessing
|
|
|
mixture of arithmetic and logic operations to measure computer system performance.
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Million Instructions Per Second (MIPS)
|
|
|
entity that creates a tailored benchmark suite for each object to be measured.
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Standard Performance Evaluation Corporation (SPEC)
|
|
|
use multiple ALUs allowing more that one instruction per clock cycle.
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Superscalar Processors
|
|
|
single instruction multiple data like video/imaging instruction; SIMD data type; MMX and SSE instructions; MMX and XMM registers.
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Vector Processing
|
|
|
special purpose processors for graphics and encryption algorithms; highly pipelined floating-point vectored and stream processing units.
|
Graphics processors units (GPU)
|
|
|
science of how heat dissipates.
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Thermodynamics
|
|
|
maximum amount of power the cooling system needs to dissipate the heat.
|
Thermal Design Power (TDP)
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