Study your flashcards anywhere!
Download the official Cram app for free >
 Shuffle
Toggle OnToggle Off
 Alphabetize
Toggle OnToggle Off
 Front First
Toggle OnToggle Off
 Both Sides
Toggle OnToggle Off
 Read
Toggle OnToggle Off
How to study your flashcards.
Right/Left arrow keys: Navigate between flashcards.right arrow keyleft arrow key
Up/Down arrow keys: Flip the card between the front and back.down keyup key
H key: Show hint (3rd side).h key
A key: Read text to speech.a key
19 Cards in this Set
 Front
 Back
Von Neumann Architecture

Has memory: stores and retrieves instructions and data
a central Processing Unit with control unit( fetch instruction from memory, decode, execute) and Arithetic Logic Unit (mathmatic calculations) input/output 

Von Neumann Bottleneck

memory speed is much slower than CPU ( 400/800 MHz at 3.8 GHz)


Fetching cycle for Von Neumann architecture

1) obtain instruction
2) Decode what fixed instuction it is 3) Operand (fetch necessary data) 4) execute 5) store result 6) repeat 

Universal Computing Architecture

* Von Neumann (by practice)
universal (tested in practice) structured (resource inefficiencies) build *Turing (by theory; standard one) universal (in theory) unstructured (resource efficient) was not, could be(?) used in practice 

Turing Machine

minimalist model of mathematical reasoning and computing
formal model of computational device to model any computable function. 

TM components

* infinite tape (memory. moves left or right)
*read/write head *finite control unit 

operations of TM

head reads symbol
head then can move left/right computational steps overwrite last symbol read moving head and output depends on 1) current symbol on tape 2) 'state of mind' of device 

Formal notation

∑ denotes the alphabet
must contain △ and cannot contain →or ← △ is the initial cell three types of transitions 

Overwrite current cell (I)

((s,a),(q,b)) if machine is in state s and current cell has a then jump to state q and write b in current cell


move right (II)

((s,a),(q,→))
if in state s and current cell has an a then jump to state q and move the header one cell to the right 

Haulting Problem

because assume that can construct a TM that could determine if any TM halted on ANY input was possible
> theoretically this cannot be possible. halting problem can be solved on many imput data but not all implication is that cannot decide whether an arbitrary input program ends in an infinite loop. 

Goedel's incompleteness theorem

Not all true statements about arithmetic are provable by any finite set of axioms


Humancomputer interface

human's function in a continuous (analog) mode
computers run in simulated discrete mode (digital) compatibility depends on the speed of digital mode (sampling of continuous signal) can represent anything if can make it into a function 

Digital Signal Processing (DSP)

is manipulation of signals using digital techniques
goes through ADC→DSP→DAC→output signal 

Analog into digital signal

sampling frequency Fs= 1/ts (s being a subunit)
if characteristic time of signal variance changes with time, data compression can be obtained with nonuniform sampling (more points at faster oscillations) 

Nyquist theorem

if the highest frequency component in a continuous sample is fm, then the signal can be sufficiently reproduced only with sampling frequency higher than 2 Fm


CPU( central processing unit)

ALU(arithmetic logic, non numerical operations)
Control Unit( performs all low level hadware operations) peripherals: external devices for sending in input or recieving output slots: interface for attaching internal devices (PCI) ports: interface for attatching external devices (USB) 

CPU registers

temporarily store data read from memory (specialized memory or general purpose)
 accessible at high speeds anything for processing is stored in registers Instruction register (IR) commands to be performed Data Registers Data input for command operations program counter: register for instructions memory buffer/data register: data traffic 

busses

collection of wires connecting together internal components of the computer to transfer data
data bus: carries actual data bits addresss bus: transfers locations where to send data control bus: carries status information advantages: versatile (allows to add new devices) and low cost disadvantages: limited speed communication bottle nect different devices need various data rates. 