Ecet 111 Test 1 Chapter 4

Front 1

PLD consisting of more than 100 interconnected SPLDs. A single chip can be programmed to implement hundreds of logic equations and operations.

Back 1

CPLD: Complex Programmable Logic Device

Front 2

Most dense form of PLD. Uses a look-up table to resolve its logic operations. Main disadvantage is that most FPGAs are volatile, losing their memory when power is removed.

Back 2

FPGA: Field-Programmable Gate Array

Front 3

Used by FPGA logic to determine output level of a circuit based on the combinations of logic levels at its inputs. Constructed as a truth table except that its outputs are only HIGH for specific combinations of inputs solving the given logic product terms.

Back 3

Look-up Table

Front 4

Internal memory is maintained even when power is removed from the IC

Back 4

Nonvolatile

Front 5

Its basic structure contains multiple inputs to several AND gates, the outputs of which are connected to a series of fixed ORs.

Back 5

PAL: Programmable Array Logic

Front 6

Its basic structure contains multiple inputs to several AND gates, the outputs of which are connected to a series of programmable ORs.

Back 6

PLA: Programmable Logic Array

Front 7

An IC containing thousands of undefined logic functions. A software development tool is used to specify (program) the specific logic to be implemented by the IC.

Also the general term used to represent PLAs, PALs, SPLDs, CPLDs, and FPGAs.

Back 7

PLD: Programmable Logic Device

Front 8

A programmable, digital logic IC containing several PAL or PLA structures with internal interconnections and memory registers.

Back 8

SPLD: Simple Programmable Logic Device

Front 9

Two or more product terms that are ORed together

(e.g., ABC + ACD + BCD)

Back 9

Sum-of-Products (SOP)