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9 Cards in this Set
- Front
- Back
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What does + mean in Verilog?
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Adder
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What does ~ mean in Verilog?
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NOT
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What does ? mean in Verilog?
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Ternary operator. Is the first value if the input is 1 and the second if the input is 0.
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What's a wire in Verilog?
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An internal variable.
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What does & mean in Verilog?
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AND
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What does ^ mean in Verilog?
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XOR
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When does a hold time violation occur?
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t_hold > t_ccq + t_cd
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When does a setup time violation occur?
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T_period < t_pcq + t_pd + t_setup
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What is the minimum clock period?
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t_pcq + t_pd + t_setup
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