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7 Cards in this Set
- Front
- Back
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Address Bus |
Group of lines to identify address |
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Data bus |
Group of lines to cary data to and from cpu |
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Control Bus |
Control info to and from CPU |
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Address valid line |
Set to invalid when idle, when cpu needs to work its set to valid |
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Read/write line |
Stores address during op |
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In clock phase 0 |
CPU puts a memory address on the address bus |
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In clock phase 1 |
the CPU takes the requested information off the data bus |
