Cis 190

Front 1

What is a motherboard?

Back 1

The motherboard is a single printed circuit board containing a number of the components of the computer. Usually it contains
 CPU and support circuits.
 RAM. (plugged into motherboard).
 I/O interface (serial and parallel ports, etc.).
 Other controller chips.
 Buses and slots for expansion cards.
 USB and FireWire connections.
 Built in graphics, sound and network capabilities and external hardware ports

Front 2

What is Parallel communication?

Back 2

Parallel communication is where several bits may be sent simultaneously, by using several communication lines in parallel.
 This makes a great deal of sense inside the computer, where we want to speed up operations as much as possible, and having a number of parallel communication lines is not very expensive.
 On the other hand, outside the computer, it can be expensive and difficult to provide such service.

Front 3

what is serial communication.

Back 3

we normally send one bit at a time, along one line, in what we call serial communication.

Front 4

What is a Bus?

Back 4

 A bus is a set of communication lines allowing data or control signals to pass between components.

Front 5

what is Semiconductor memory ?

Back 5

• Semiconductor memory is an integrated circuit containing millions of transistors.
 Each bit of memory takes one or more transistors.
 Transistor can be in one of two states.
 The state it is in represents a 0 or a 1.
 Can be maintained in that state with a small amount of electricity.
 State lost when power goes off (it is volatile).

Front 6

What is Access time?

Back 6

• Access time is important - how long does it take to read a bit of memory?
 Hard disk memory access time measured in milliseconds (thousandths of a second).
 1953 IBM ad: drum memory can be recalled in 1/40,000 of a second.
 Core memory - measured in microseconds (millionths of a second).
 Modern RAM access time is measured in nanoseconds (billionths of a second).

Front 7

What is Dynamic RAM ?

Back 7

• Dynamic RAM (DRAM) requires a periodic electrical charge to keep the state of a bit.
 Without this “refreshing” charge, it loses its state and forgets.

Front 8

What is Static RAM ?

Back 8

• Static RAM (SRAM) is larger (more transistors), faster, and more complicated (and of course more expensive).
 Still requires the power to be on, but does not need a frequent refreshing charge.
 Main memory usually uses a type of DRAM.
 Cache memory usually uses SRAM.

Front 9

What is Bus size?

Back 9

• Bus size - controls how long it takes to move data around.
 8-bit bus can carry one byte at a time.
 16-bit bus can carry two bytes at a time.
 64-bit bus can carry eight bytes at a time.
 With an 8-bit bus, it takes four operations to move a four byte integer.

Front 10

What is word size?

Back 10

• Word size - number of bits the computer can process at a time.
 Usually corresponds to size of registers in CPU.
 An 8-bit CPU can only add 8 bits at a time.
 Adding two 32-bit numbers will take four operations.
 Intel defines a word as 16 bits, so for them, 32 bits is a double word, and 64 is a quad word, etc.
• Generally makes sense for word and bus size to be the same.
 Not all architectures have done this.

Front 11

ASCII

Back 11

 ASCII encoding used 7 bits originally. If used in an 8-bit byte, the extra bit could be used for error detection, or to provide more characters (28, or 256).

Front 12

EBCDIC

Back 12

 EBCDIC uses 8 bits.

Front 13

“How many bits would we need (at least) to have an 5000 memory addresses

Back 13

 To what power do we have to raise 2 to get 5000?
 log¬2 5000 = 12.28771238…
 That’s how many bits we would need (we figured the answer out as 13).
log2 n = log10 n / log10 2 (or log2 n = ln n / ln 2).

Front 14

What is the cycle of the CPU?

Back 14

1. Fetch - the instruction at the address in RAM indicated by the instruction pointer into the instruction register.
2. Increment - the instruction pointer.
3. Execute - the instruction in the instruction register (after decoding).

Front 15

What is a jump instruction?

Back 15

• A program does not usually execute all of its instructions sequentially.
• When a program’s logic indicates it should branch to another section of code in RAM, it uses some type of jump (also called branch) instruction.
• A jump instruction resets the instruction pointer to the address of the next desired instruction.

Front 16

How do you speed up the CPU?

Back 16

Speeding up the CPU.
• Notice how CPUs are made faster:
1. Speed up the clock – we can only speed it up so much.
2. Do more in each clock tick - pipelining and superscalar (many pipelines), then dual and quad cores.
3. Speed up anything else that slows down operations - memory accesses, video display, etc.

Front 17

Explain memory addressing

Back 17

• Remember we saw how the number of bits used for an address determines how many addresses are possible.
• CPU can only specify so many locations in RAM, depending on how many bit addresses are used.
 16-bit addressing restricts you to 65,536 addresses (64 KB of RAM).
 32-bit addressing restricts you to 4,294,967,296 (4 GB of RAM).
 64-bit addressing allows 18,446,744,073,709,551,616 bytes of RAM.
• Don’t confuse this with hard disk access and sizes - a different means of addressing is used there (we don’t have an address for every byte).

Front 18

what is protected mode

Back 18

• Protected mode provided hardware protection for sections of memory.
 Programs could only access inside their defined memory areas.
 An attempt to range elsewhere would result in operating system shutting down program before it caused damage to another program.

Front 19

what is real mode?

Back 19

• Real mode is the old 8086/8088 1 megabyte unprotected memory system.
 Though the 80286 could access 16 MB of memory in protected mode, it had to be backwards compatible with the 8086/8088.
 Lots of software written for this mode.

Front 20

80286

Back 20

80286
• Introduced in 1982.
• Used in the 1984 PC AT (Advanced Technology).
• Ran 5 to 6 times faster than 8088.
• Increased 24-bit address space (224 = 16,777,216) allowed up to 16MB of RAM.
• Better memory management - protected mode and virtual memory.

Front 21

80386

Back 21

80386
 32 bit internal and external buses.
Improvements
• Processor now faster than memory access time.
• Used bank interleaved memory (simultaneous access of multiple memory blocks) and cache memory.
• Main memory attached to processor’s local (external) bus.
• Allowed full linear addressing model - without segment registers.
• 32-bit addressing allowed up to 4 GB RAM.

Front 22

80486

Back 22

80486
• Level 1 cache memory on the chip.
 Level 1 (L1) cache is inside CPU chip.
 Level 2 (L2) cache is outside CPU chip.
• One micron technology (transistors with dimensions as small as 1 micron).
 Means you can get them closer.
 Can use lower power.
 Less delay along connections.
 Faster speeds possible.
• 486 used some RISC (more on RISC later) features.

Front 23

Pentium

Back 23

Pentium
• Introduced in March 1993 with 3.1 million transistors.
• 32-bit processor.
• Faster built-in math coprocessor (3 to 10 times faster).
• 16 KB L1 split cache.
• First Pentiums at 60 and 66 MHz.
• Local bus 64 bits wide at 60 (some early Pentiums) and 66 MHz.
• More RISC concepts in processor.

Pentium L1 Split Cache
• 16 KB total - 8 KB for instructions, 8 KB for data.
• Two-way set-associative design for each cache.
• Output of instruction cache feeds prefetch stage of CPU over 256-bit bus.
Pentium Local (External) Bus
• 64 bits wide, running at 66 MHz.
• Burst block transfer mode.
• Address pipelining - allows two outstanding bus transactions.
 Can be decoding next address while current transfer still occurring.

Front 24

What is Parity Checking?

Back 24

• Parity checking: setting one (extra) bit to either one or zero so that the total number of ones in a byte or word is either even (or odd).
• This will help detect a random series of bit errors, unless a combination of errors leaves the parity bit still appearing correct, e.g.
 A 1 becomes a 0, and another 0 becomes a 1 - total number of 1s is still the same.
 Two 0s become 1s or two 1s become 0s- number of 1s is still even.

Front 25

Pentium Pro (P6, or 80686)

Back 25

• Onboard L2 cache connected directly to CPU core by 64-bit bus running at processor clock speed (not processor local bus speed of 60-66 MHz).
 Called dual independent bus architecture (DIB).
• Offered at 166, 180 and 200 MHz speeds (Sept. 1997).
• Cache is ECC protected - uses error correcting code to catch errors.
• Can maintain L2 cache coherency with up to 4 processors.
• Superscalar with three pipelines.
• 12-stage pipelined architecture versus Pentium’s 5 stages.
 Means the number of stages an instruction is divided into for pipelining.
 More stages = smaller time per stage = more instructions per clock cycle get finished.
 Pipeline process time reduced by 30% over Pentium.
• Processor can look ahead into instructions and find work to do to keep busy.
• Called dynamic execution, and uses:
 Multiple branch prediction: figure out what branches can occur and prepare instructions from both directions of a branch.
 Data-flow analysis: determine dependencies b

Front 26

Pentium II

Back 26

• Introduced summer 1997, .35 micron technology, 7.5 million transistors.
• Essentially an improvement on the Pentium Pro.
• Can execute up to five instructions at a time [Intel Web Site].
• Built-in MMX support.
• Higher clock speeds: 233, 266, and 300 MHz initially.
 Now also 350, 400 and 450 (.25 micron technology) MHz.
• Dual independent bus architecture, like the Pentium Pro (L2 cache connects at CPU clock speed).
 L2 cache bus and main memory external system bus.
 Processor can access both buses simultaneously if needed.
• L1 cache increased to 32 Kbytes and is a split cache (16 KB each for data and instructions).
• 512 KB L2 cache.
• Single Edge Contact (SEC) cartridge (called slot 1) mounting.
 Size of a Nintendo cartridge.
 Sits in a slot on the motherboard - takes up less space on it.
 Contains processor, caches and core logic.
 Allows static RAM for L2 cache, and lower price.
 Older Pentium sockets called “socket 7”.
• Runs older 16-

Front 27

Directed-mapped caches

Back 27

* Directed-mapped caches keep only one set of data from often-used memory areas.
* Simple to design, effective when cache large.

Front 28

Set-associative caches

Back 28

* Set-associative caches keep data from more than one area of often used memory.
* Two-way, four-way and eight-way set-associative caches implemented.
* Can be very effective with small cache memory sizes.
* 16 KB four-way set-associative cache can outperform a 64 KB or 128 KB direct-mapped cache.
* L1 caches are usually set-associative.

Front 29

Write back (or copy-back) cache

Back 29

• Write back (or copy-back) cache stores writes back to memory until convenient, rather than do a write to slow DRAM.
 Must detect memory accesses to changed locations and hold off read until memory is updated.

Front 30

Write-through cache

Back 30

• Write-through cache does a write to DRAM each time a write occurs, which slows down the cache.
 Memory writes always happen at slower DRAM speed.

Front 31

Unified cache

Back 31

• Unified cache uses single cache memory for instructions and data.

Front 32

Split cache

Back 32

• Split cache separates cache memory into sections for instructions and data.
 Can be addressed simultaneously.
 Modern CPUs tend to have three independent caches for instructions, data and a translation look-aside buffer for virtual-to-physical address translation.

Front 33

Bus Width

Back 33

Bus Width (Size)
• The number of lines used for addresses or data determines how the bus performs and its limitations.
• E.g. 8-bit data bus means we can only transmit one byte at a time.
• 20 lines for address means we are limited to 220 addresses (bytes of RAM).
• Bus usually described by data width, e.g. 64-bit bus means 64 data lines.

Front 34

Bus mastering

Back 34

• Bus mastering allows transfers between peripherals at maximum bus rates.

Front 35

Stacks

Back 35

• When CPU is interrupted, it has to put work aside to deal with something else.
• It must save the state of the work that was interrupted.
• The registers can be saved in the stack.
• Think of the stack like a pile of books.
 The most recent book you added is at the top.
 When you add a book to the top of the stack, you are saving your current work.
 When you remove a book from the top of the stack, you are retrieving your most recent work.
• Now just imagine saving the state of all the registers in a book and putting it on top of the stack.
• When the interruption is over, you can retrieve it.
• Note that this mechanism allows interruptions of interruptions.
• Each interruption results in another book on the stack.
• You take them off in reverse order, dealing with each.
• Eventually you get back to the original (bottom) book (task).
• When registers are restored, it appears that no interruption has occurred.

Front 36

Polling

Back 36

• Polling is where the CPU periodically checks to see whether anything has happened.
 Like occasionally asking everyone in the class, one at a time, whether they have anything to say.
 Wasteful, especially in a multitasking environment, where CPU could be doing something else.

Front 37

Interupts

Back 37

• Interrupts is where other devices can send the CPU a signal that they have something to say.
 Like putting up your hand in class.

Front 38

DMA

Back 38

• Some boards need to transfer data directly to system memory (RAM).
 Done with a direct memory access (DMA) channel.