Chapter 6 (Unit 3)

Front 1

A __________ is the communication channel that connects all computer system components.

Back 1

bus or system bus

Front 2

Cache types that are generally implemented on the same chip as the CPU include __________ and__________.

Back 2

L1 or level one, and L2 or level two

Front 3

The CPU is always capable of being a(n) __________, thus controlling access to the bus by all other devices in the computer system.

Back 3

bus master

Front 4

A(n) __________ is a reserved area of memory used to resolve differences in data transfer rate or data transfer unit size.

Back 4

buffer

Front 5

A(n) __________ is an area of fast memory where data held in a storage device is prefetched in anticipation of future requests for the data.

Back 5

cache

Front 6

A cache controller is a hardware device that initiates a(n) __________ when it detects a cache miss.

Back 6

cache swap

Front 7

The __________ transmits command, timing, and status signals between devices in a computer system

Back 7

control bus

Front 8

If possible, the system bus __________ rate should equal the CPU’s speed.

Back 8

clock

Front 9

The __________ is a special-purpose register that always points to the next empty address in the stack

Back 9

stack pointer

Front 10

The __________ transfers control to the interrupt handler at the memory address corresponding to theinterrupt code.

Back 10

supervisor

Front 11

The set of register values stored in the stack while processing an interrupt is also called the __________.

Back 11

machine state

Front 12

A(n) __________ is a program stored in a separate part of primary storage to process a specific interrupt.

Back 12

interrupt handler

Front 13

During interrupt processing, register values of a suspended process are held on the __________.

Back 13

stack

Front 14

A(n) __________ is a signal to the CPU or OS that some device or program requires processing services.

Back 14

interrupt

Front 15

A(n) __________ is a simple processor that intervenes when two devices want control of the bus at the same time.

Back 15

bus arbitration unit

Front 16

The __________ has a much higher data transfer rate than the system bus because of its shorter length, higher clock rate, and large number of parallel communication lines.

Back 16

memory bus

Front 17

The CPU incurs one or more __________ if it’s idle pending the completion of an I/O operation.

Back 17

I/O wait states

Front 18

The system bus can be divided logically into four sets of transmission lines: the __________ bus, the__________ bus, the _ bus, and the __________ bus.

Back 18

address, control, data, power

Front 19

During a(n) __________ operation, one or more register values are copied to the top of the stack. Duringa(n) __________ operation, one or more values are copied from the top of the stack to registers.

Back 19

push, pop

Front 20

The comparative size of a data set before and after data compression is described by the compression__________.

Back 20

ratio

Front 21

If data isn’t exactly the same as the original after compressing and decompressing, the compressionalgorithm is said to be __________. If data is the same as the original after compressing anddecompressing, the compression algorithm is said to be __________.

Back 21

lossy, lossless

Front 22

A(n) __________ is a special-purpose processor dedicated to managing cache content.

Back 22

cache controller

Front 23

A(n) __________ is a communication pathway from the CPU to a peripheral device.

Back 23

I/O port

Front 24

A(n) __________ is implemented using main memory, improves file I/O performance and is controlled by the operating system .

Back 24

file cache

Front 25

The _________________ transmits a memory address when primary storage is the sending or receivingdevice

Back 25

address bus

Front 26

The CPU and bus normally view any storage device as a(n) __________, ignoring the device’s physical storage organization.

Back 26

linear address space

Front 27

Part of a device controller’s function is to translate __________ into physical accesses.

Back 27

logical accesses

Front 28

A(n) __________ controller assumes the role of bus master for all transfers between memory and other storage or I/O devices, leaving the CPU free to execute computation and data movement instructions.

Back 28

DMA

Front 29

When a read operation accesses data already contained in the cache, it’s called a(n) __________.

Back 29

cache hit

Front 30

The __________ defines the format, content, and timing of data, memory addresses, and control messagessent across the bus.

Back 30

bus protocol

Front 31

In __________ architecture, multiple CPUs and cache memory are embedded on a single chip.

Back 31

multicore

Front 32

The term __________ describes methods of increasing processing and other computer system power byusing larger and more powerful computers.

Back 32

scaling up

Front 33

__________ architecture is a cost-effective approach to computer system design when a single computerruns many different applications or services at once.

Back 33

multiple-processor

Front 34

Examples of a(n) __________ bus include SATA and SCSI.

Back 34

storage