2.1 Goals
The goals of this internship are:
a. Provide a solution which reduces the stall time and increases the system efficiency.
b. A solution which could be generalized in future to be used with more than two sub-systems.
2.2 Solution Overview
The most common solution to such a problem is by making use of a buffer.
“A buffer often adjusts timing by implementing a queue (or FIFO) algorithm in memory, simultaneously writing data into the queue at one rate and reading it at another rate.”[2]
The simplest form of buffer that could be used in between the two sub-systems is a FIFO. But a simple on chip FIFO could not solve this problem entirely as the amount of available FIFO on a particular FPGA is very less.
Hence, a simple external RAM module is used for this purpose. There is a memory controller (MIG) designed by Xilinx and available as an IP core for the system designers to use to communicate with the RAM. But, it is only possible for a single system to communicate with a single MIG which in turn communicates with the RAM module. …show more content…
This gave birth to the Data Flow Controller (DFC) module. The job of the DFC is to appropriately route the data between the two sub-systems and RAM as and when requested.
2.3 Related Work
[3] is one of the work which introduces the idea of a Memory Management Unit. “MMU allows multiple tasks to concurrently use external RAM banks.”
[4] is another piece of work which also introduces the use of “a memory arbiter system capable of allowing two systems to communicate to the same DDR3 SDRAM
The goals of this internship are:
a. Provide a solution which reduces the stall time and increases the system efficiency.
b. A solution which could be generalized in future to be used with more than two sub-systems.
2.2 Solution Overview
The most common solution to such a problem is by making use of a buffer.
“A buffer often adjusts timing by implementing a queue (or FIFO) algorithm in memory, simultaneously writing data into the queue at one rate and reading it at another rate.”[2]
The simplest form of buffer that could be used in between the two sub-systems is a FIFO. But a simple on chip FIFO could not solve this problem entirely as the amount of available FIFO on a particular FPGA is very less.
Hence, a simple external RAM module is used for this purpose. There is a memory controller (MIG) designed by Xilinx and available as an IP core for the system designers to use to communicate with the RAM. But, it is only possible for a single system to communicate with a single MIG which in turn communicates with the RAM module. …show more content…
This gave birth to the Data Flow Controller (DFC) module. The job of the DFC is to appropriately route the data between the two sub-systems and RAM as and when requested.
2.3 Related Work
[3] is one of the work which introduces the idea of a Memory Management Unit. “MMU allows multiple tasks to concurrently use external RAM banks.”
[4] is another piece of work which also introduces the use of “a memory arbiter system capable of allowing two systems to communicate to the same DDR3 SDRAM